1. Field of the Inventions
The present invention relates to bias circuits and specifically to global biasing circuits using resistor calibration circuits.
2. Background Information
Low power dissipation is extremely critical for many applications for radio frequency (RF) and analog integrated circuits. These applications include battery powered devices, universal serial bus (USB) compatible devices, and even set top box products. Lower power solutions extend battery life and allow more functionality to be integrated into smaller packages for highly integrated products. The term integrated circuit (IC) is often used interchangeable with the term “chip.”
Many low power solutions address the issue of power consumption with new circuit topologies that offer similar performance with reduced current consumption. While some variation is expected from the off-chip supply voltage, the current consumption under nominal process conditions sets the nominal power dissipation. However, the power budget for IC products is nearly always based upon a worst case power budget. The worst case power is a function of process, voltage, and temperature variations within the chip under the specified range of operating conditions.
Almost all analog and RF circuits use a bias circuit as a supply independent reference to generate bias voltages or currents. The supply independent nature of these reference circuits eliminates variation in the overall current consumption due to variation in the supply voltage. Conceptually, bias currents essentially operate by using a reference voltage which is fixed to a physical characteristic such as the bandgap voltage of a transistor and converting it to a current using a resistor in accordance with Ohm's law. As the current consumption variation due to supply voltage is eliminated, the remaining significant source of current variation is in the variability of the resistors in the bias circuits. Unfortunately, the tolerances of on-chip resistors are very great due to process variations. These resistors can have tolerances as large as +/−15% in a typical silicon process. Since the bias currents are often directly proportional to these resistances, this variation results in as much as 15% additional power dissipation under worst case conditions due just to the tolerances of the resistors. For example, a silicon tuner with a nominal power dissipation of 1.5 W, may have worst case power dissipation as high as 1.725 W. The result is an additional power penalty of 225 mW that must be built into the power budget for the chip to cover worst case operating conditions. The additional 225 mW is higher than the individual nominal power dissipation of many of the most power hungry circuits on the chip.
While the tolerance of on-chip resistors is limited by process variation to the range of 10-15%, off-chip resistors are typically available with much tighter tolerances. Therefore, it is desirable for the on-chip bias circuits to reference high precision, off-chip resistors whenever possible. This poses problems for highly integrated RF or analog integrated circuits which typically use many different custom bias circuits in multiple separate supply domains. Referencing any bias circuit to an off-chip resistor requires a designated package pin for each individual resistor. Package pins are often very limited and are used mainly for power supplies and I/O pins. Therefore, the number of high precision, off-chip resistors that can be used for separate, local bias circuits is very limited. Additional off-chip resistors also add to the bill of materials (BOM) for the IC product which increases the cost.
There are several strategies commonly used in the past for global biasing using integrated resistors in RF or analog integrated circuits. The first approach is to use a single common shared global bias circuit. FIG. 1 shows an integrated circuit with a shared, common global bias circuit. With this approach, there is one common bias circuit that feeds all the analog circuits within the chip by feeding either a bias current or a bias voltage to each analog circuit in their individual supply domains. Distribution of bias currents is most commonly used since the currents are less sensitive to picking up common mode noise; however, bias voltages can be used as well. Common global bias circuits offer the advantage of one, high precision bias circuit that can be generated by using one off-chip high precision resistor. In this way, tolerance on the bias currents as good as +/−1% is easily achievable at the cost of only one designated package pin and one off-chip high precision resistor.
Unfortunately, the common global bias approach suffers from the drawback that that the common global bias circuit allows spurs and noise to couple through the bias circuit from noisy analog circuits, like the crystal oscillator, to very sensitive circuits like the low noise amplifier (LNA). Coupling can occur though the shared supply voltage (VCC). Coupling also is very likely to occur through the metal routing used to carry bias currents from the global bias circuit to each individual analog circuit. The metal routing for the bias currents originating from one common global bias on any highly integrated RF or analog ICs will typically span several hundred microns. This routing may be required to pass near many different circuits where it can pick up noise at any point along the way. For example, in FIG. 1, analog circuit 102 could be a crystal oscillator and analog circuit 106 could be an LNA. Noise introduced by analog circuit 102 could travel to analog circuit 106 through the Ibias1 and Ibias3 lines through global current bias circuit 110. Therefore, the common global bias approach is extremely prone to spreading noise around the chip and limiting the performance of sensitive analog circuits.
Another drawback suffered by the common global bias approach is that the bias circuit cannot be optimized for design constraints of all analog circuits simultaneously. Each analog circuit has a different preferred topology to optimize the performance of that individual block. Some analog circuits are very sensitive to 1/f noise, such as a crystal oscillator or the charge pump in a phase-locked loop for example. In other analog circuits, the thermal noise floor established by the bias circuit is the most critical such as in a LNA or RF mixer. Also, the temperature coefficient (TC) requirements may vary for different analog circuits. Some analog circuits require a proportional to absolute temperature (PTAT) current, while others require a bandgap (BG) current with flat TC. A common global bias circuit optimized for one set of individual performance requirements of one analog circuit would likely produce suboptimal performance in another analog circuit having different performance requirements. Common global biasing with one circuit prevents optimization of the bias for individual performance requirements of any one analog circuit. Therefore, the performance of the individual analog circuits generally cannot be fully optimized and may not even meet the required specifications.
A second global biasing approach is to use individual bias circuits, optimized for each individual analog circuit block. A block diagram of this approach is illustrated in FIG. 2. This is the biasing scheme used on many silicon tuners. With the individual biasing scheme, the biasing for each of the analog circuit blocks is optimized separately for the very best performance. The bias circuits, for example, include PTAT bias circuits, band gap referenced bias circuits, and a low 1/f noise Widlar-based bias circuit. The main drawback to this approach is the large process variation of the on-chip resistors. For example, analog circuit 222 could be coupled to bias circuit 202 which may be a PTAT bias circuit and analog circuit 224 could be coupled to bias circuit 204 which may be a band gap referenced bias circuit whereas bias circuit 206 could be a low 1/f noise Widlar-biased bias circuit which is coupled to 1/f noise sensitive analog circuit 226. In this manner, bias circuits can be optimized for the best performance of the coupled analog circuit.
However, with many separate bias circuits, it becomes impractical to use off-chip resistors for each one due to the limited number of pins on the IC package. Therefore, the bias currents are generated with reference to on-chip resistors and result in large process variation as high at +/−15% in a typical silicon IC process technology. This adds potentially 15% to the current consumption and 15% to the power dissipation of the full chip. For example, a +15% lower on-chip sheet resistance for a 1.5 W silicon tuner nominally consuming 430 mA can consume up to 495 mA. This represents an extra 65 mA of current and 215 mW higher power dissipation. The extra 65 mA is comparable to adding an additional analog circuit with significant current consumption to the die.
A third approach represents a hybrid to the two previous approaches where a combination of an on-chip resistor referenced bias circuits and an off-chip, high precision resistor referenced bias circuits. This scheme is also popular for many RF and analog integrated circuits. The variation in the global current dissipation is reduced since a few of the bias circuits are referenced to the off-chip resistor. Each analog circuit can have its own separate bias circuit fully optimized for the performance of that particular circuit. At the same time, one or two off-chip resistors can help tighten the current tolerance on a few of the most power hungry blocks on the chip, thereby minimizing the power consumption of the whole chip.
FIG. 3 depicts an example of the hybrid biasing approach. Analog circuits 322, 324, 326, 328, 330, and 332 are coupled to corresponding bias circuits 302, 304, 306, 308, 310, and 312, respectively. In this example, analog circuits 322, 324, and 330 are particularly power hungry circuits, so their corresponding bias circuits 302, 304 and 310 use high precision off-chip reference resistors 350, 352, and 354, respectively, to reference the circuits.
Though this approach offers some of the advantages of the other approaches, there are some disadvantages as well. The first disadvantage is that most of the analog circuits on the full chip are still referenced to on-chip resistors, with the exception of a very few circuits where the high precision off-chip resistors are used. The number of these circuits is limited by the package pins that are free to allocate to these bias circuits. Another disadvantage is that the bias circuit referenced to the off-chip resistor directly feeds one or more sensitive analog circuits. In this way, the bond wire, package pin, and metal routing used to connect the external resistance can pick up noise within the chip, within the package or on the printed circuit board (PCB) and spread it to the circuits which use the bias currents. Noise may also arise in highly integrated chips due to the floor plan when external resistors are used for biasing. The floor plan often requires that one or more analog circuits be placed in the center of the chip. For those circuits, metal traces to connect an off-chip resistor must be routed close to other potentially noisy circuits to reach the pad ring on the perimeter of the die. As an example, in a silicon tuner, the baseband amplifiers might be located in the center of the die, and they are referenced to an off-chip resistor. The traces to connect the bias circuit to the pad ring for the external resistor are routed by the voltage controlled oscillators (VCO) inductors. The inductors carry high currents and can easily induce a voltage on the metal traces, disturbing the value of the bias currents. This change in bias current can easily affect the gain and other performance of the analog baseband circuits.
Given these constraints, there is a considerable need for a circuit and method of referencing the on-chip bias circuits to one high precision off-chip resistor using only one designated package pin. Further, there is considerable motivation for a circuit and method of distributing a higher precision resistance globally across the IC without picking up common mode noise and spreading it from a noisy circuit to a sensitive one. Accordingly, various needs exist in the industry to address the aforementioned deficiencies and inadequacies.